By Mikhail Kovalev, Silvia M. Müller, Wolfgang J. Paul
This monograph is predicated at the 3rd author's lectures on laptop structure, given in the summertime semester 2013 at Saarland college, Germany. It incorporates a gate point building of a multi-core computing device with pipelined MIPS processor cores and a sequentially constant shared memory.
The e-book includes the 1st correctness proofs for either the gate point implementation of a multi-core processor and likewise of a cache established sequentially constant shared reminiscence. This opens easy methods to the formal verification of synthesizable for multi-core processors within the future.
Constructions are in a gate point version and hence deterministic. by contrast the reference types opposed to which correctness is proven are nondeterministic. the advance of the extra equipment for those proofs and the correctness evidence of the shared reminiscence on the gate point are the most technical contributions of this work.
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Extra resources for A Pipelined Multi-core MIPS Machine: Hardware Implementation and Correctness Proof
N-bit zero tester a a b b n n n n n n-eq 1 n-Zero 1 eq neq 1 eq (a) symbol 1 neq (b) implementation Fig. 13. n-bit equality tester The inputs a[n − 1 : 0], b[n − 1 : 0] and outputs eq, neq of an n-bit equality tester in Fig. 13 satisfy eq ≡ a = b , neq ≡ a = b . The implementation uses neq(a[n − 1 : 0]) = nzero(a[n − 1 : 0] ⊕ b[n − 1 : 0]) , eq = neq . An n-decoder is a circuit with inputs x[n − 1 : 0] and outputs y[2n − 1 : 0] satisfying ∀i : yi = 1 ↔ x = i . A recursive construction with k = one argues in the induction step n 2 is shown in Fig.
Proof. The direction from left to right is trivial. For the other direction we distinguish cases: • • e(a) = 1. Then e (a) = 1 by hypothesis. e(a) = 0. Then e (a) = 1 would by hypothesis imply the contradiction e(a) = 1. Because in Boolean algebra e (a) ∈ B we conclude e (a) = 0. Thus, we have e(a) = e (a) for all a ∈ Bn . 1 Identities In this section we provide a list of useful identities of Boolean algebra. 6 Boolean Algebra 25 Table 4. Verifying the ﬁrst of de Morgan’s laws x1 0 0 1 1 • x1 ∧ x2 0 0 0 1 x2 0 1 0 1 x1 ∧ x2 1 1 1 0 x1 1 1 0 0 x2 1 0 1 0 x1 ∨ x2 1 1 1 0 De Morgan’s laws: x1 ∧ x2 ≡ x1 ∨ x2 x1 ∨ x2 ≡ x1 ∧ x2 Each of these identities can be proven in a simple brute force way: if the identity has n variables, then for each of the 2n possible substitutions of the variables the left and right hand sides of the identities are evaluated with the help of Table 3.
2. 1 In the design from  the glitches can be produced on the instruction memory address by the multiplexer between pc and dpc as described in Chap. 7. 1 Digital Gates and Circuits ab ab a a∧b a∨b b a a⊕b a ¯ 31 Fig. 2. Symbols for gates in circuit schematics 1 Inputs 0 x0 x1 ... xn−1 wires and gates y0 y1 Outputs ... yt−1 Fig. 3. Illustration of inputs and outputs of a circuit C A circuit C consists of a ﬁnite set G of gates2 , a sequence of input signals x[n − 1 : 0], a set N of wires that connect them, as well as a sequence of output signals y[t − 1 : 0] ⊆ Sig(C) chosen from all signals of circuit C (as illustrated in Fig.